// ****************************************************************************** 
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  sdmam_ch_regs_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2021/10/23 09:19:00 Create file
// ******************************************************************************

#ifndef __SDMAM_CH_REGS_REG_OFFSET_FIELD_H__
#define __SDMAM_CH_REGS_REG_OFFSET_FIELD_H__

#define SDMAM_CH_REGS_CH_QUIESCENT_LEN            1
#define SDMAM_CH_REGS_CH_QUIESCENT_OFFSET         31
#define SDMAM_CH_REGS_CH_TLBI_EN_LEN              1
#define SDMAM_CH_REGS_CH_TLBI_EN_OFFSET           23
#define SDMAM_CH_REGS_CH_MERGE_DOORBELL_EN_LEN    1
#define SDMAM_CH_REGS_CH_MERGE_DOORBELL_EN_OFFSET 22
#define SDMAM_CH_REGS_CH_AUTO_MERGE_EN_LEN        1
#define SDMAM_CH_REGS_CH_AUTO_MERGE_EN_OFFSET     21
#define SDMAM_CH_REGS_SAFETY_CHECK_EN_LEN         1
#define SDMAM_CH_REGS_SAFETY_CHECK_EN_OFFSET      20
#define SDMAM_CH_REGS_CH_FSM_STATUS_LEN           4
#define SDMAM_CH_REGS_CH_FSM_STATUS_OFFSET        16
#define SDMAM_CH_REGS_CH_CQE_EN_LEN               1
#define SDMAM_CH_REGS_CH_CQE_EN_OFFSET            15
#define SDMAM_CH_REGS_SMMU_BYPASS_EN_LEN          1
#define SDMAM_CH_REGS_SMMU_BYPASS_EN_OFFSET       14
#define SDMAM_CH_REGS_CH_QOS_LEN                  4
#define SDMAM_CH_REGS_CH_QOS_OFFSET               10
#define SDMAM_CH_REGS_CH_MODE_LEN                 1
#define SDMAM_CH_REGS_CH_MODE_OFFSET              9
#define SDMAM_CH_REGS_CH_AXPORT_NS_LEN            1
#define SDMAM_CH_REGS_CH_AXPORT_NS_OFFSET         8
#define SDMAM_CH_REGS_CH_INVALL_LEN               1
#define SDMAM_CH_REGS_CH_INVALL_OFFSET            7
#define SDMAM_CH_REGS_CH_RETRY_LEN                1
#define SDMAM_CH_REGS_CH_RETRY_OFFSET             6
#define SDMAM_CH_REGS_CH_ABORT_EN_LEN             1
#define SDMAM_CH_REGS_CH_ABORT_EN_OFFSET          5
#define SDMAM_CH_REGS_CH_NS_LEN                   1
#define SDMAM_CH_REGS_CH_NS_OFFSET                4
#define SDMAM_CH_REGS_CH_RESET_LEN                1
#define SDMAM_CH_REGS_CH_RESET_OFFSET             3
#define SDMAM_CH_REGS_CH_PAUSE_RESUME_LEN         1
#define SDMAM_CH_REGS_CH_PAUSE_RESUME_OFFSET      2
#define SDMAM_CH_REGS_CH_PAUSE_LEN                1
#define SDMAM_CH_REGS_CH_PAUSE_OFFSET             1
#define SDMAM_CH_REGS_CH_ENABLE_LEN               1
#define SDMAM_CH_REGS_CH_ENABLE_OFFSET            0

#define SDMAM_CH_REGS_TYPER_QRS_LEN            1
#define SDMAM_CH_REGS_TYPER_QRS_OFFSET         4
#define SDMAM_CH_REGS_TYPER_SRS_LEN            1
#define SDMAM_CH_REGS_TYPER_SRS_OFFSET         3
#define SDMAM_CH_REGS_TYPER_RAS_LEN            1
#define SDMAM_CH_REGS_TYPER_RAS_OFFSET         2
#define SDMAM_CH_REGS_TYPER_DISTRIBUTED_LEN    1
#define SDMAM_CH_REGS_TYPER_DISTRIBUTED_OFFSET 1
#define SDMAM_CH_REGS_TYPER_SQ_ABORT_LEN       1
#define SDMAM_CH_REGS_TYPER_SQ_ABORT_OFFSET    0

#define SDMAM_CH_REGS_CH_ERR_STATUS_LEN    8
#define SDMAM_CH_REGS_CH_ERR_STATUS_OFFSET 20
#define SDMAM_CH_REGS_CH_IOE_STATUS_LEN    1
#define SDMAM_CH_REGS_CH_IOE_STATUS_OFFSET 17
#define SDMAM_CH_REGS_CH_IOC_STATUS_LEN    1
#define SDMAM_CH_REGS_CH_IOC_STATUS_OFFSET 16

#define SDMAM_CH_REGS_CH_IOE_MASK_LEN    1
#define SDMAM_CH_REGS_CH_IOE_MASK_OFFSET 1
#define SDMAM_CH_REGS_CH_IOC_MASK_LEN    1
#define SDMAM_CH_REGS_CH_IOC_MASK_OFFSET 0

#define SDMAM_CH_REGS_CH_MEMATTR_LEN    8
#define SDMAM_CH_REGS_CH_MEMATTR_OFFSET 2
#define SDMAM_CH_REGS_CH_SNP_LEN        2
#define SDMAM_CH_REGS_CH_SNP_OFFSET     0

#define SDMAM_CH_REGS_CQE_STATUS_LEN    16
#define SDMAM_CH_REGS_CQE_STATUS_OFFSET 1
#define SDMAM_CH_REGS_COMPLETION_LEN    1
#define SDMAM_CH_REGS_COMPLETION_OFFSET 0

#define SDMAM_CH_REGS_SQ_BA_L_LEN    32
#define SDMAM_CH_REGS_SQ_BA_L_OFFSET 0

#define SDMAM_CH_REGS_SQ_BA_H_LEN    16
#define SDMAM_CH_REGS_SQ_BA_H_OFFSET 0

#define SDMAM_CH_REGS_SQ_SHAREABILITY_LEN    2
#define SDMAM_CH_REGS_SQ_SHAREABILITY_OFFSET 20
#define SDMAM_CH_REGS_SQ_CACHEABILITY_LEN    3
#define SDMAM_CH_REGS_SQ_CACHEABILITY_OFFSET 16
#define SDMAM_CH_REGS_SQ_SIZE_LEN            16
#define SDMAM_CH_REGS_SQ_SIZE_OFFSET         0

#define SDMAM_CH_REGS_SQ_TDB_LEN    16
#define SDMAM_CH_REGS_SQ_TDB_OFFSET 0

#define SDMAM_CH_REGS_SQ_HDB_LEN    16
#define SDMAM_CH_REGS_SQ_HDB_OFFSET 0

#define SDMAM_CH_REGS_CQ_BA_L_LEN    32
#define SDMAM_CH_REGS_CQ_BA_L_OFFSET 0

#define SDMAM_CH_REGS_CQ_BA_H_LEN    16
#define SDMAM_CH_REGS_CQ_BA_H_OFFSET 0

#define SDMAM_CH_REGS_CQ_SHAREABILITY_LEN    2
#define SDMAM_CH_REGS_CQ_SHAREABILITY_OFFSET 20
#define SDMAM_CH_REGS_CQ_CACHEABILITY_LEN    3
#define SDMAM_CH_REGS_CQ_CACHEABILITY_OFFSET 16
#define SDMAM_CH_REGS_CQ_SIZE_LEN            16
#define SDMAM_CH_REGS_CQ_SIZE_OFFSET         0

#define SDMAM_CH_REGS_CQ_TDB_LEN    16
#define SDMAM_CH_REGS_CQ_TDB_OFFSET 0

#define SDMAM_CH_REGS_CQ_HDB_LEN    16
#define SDMAM_CH_REGS_CQ_HDB_OFFSET 0

#define SDMAM_CH_REGS_CH_ICDT_OSTD_TH_LEN    32
#define SDMAM_CH_REGS_CH_ICDT_OSTD_TH_OFFSET 0

#define SDMAM_CH_REGS_BOTH_NAN_MASK_LEN       1
#define SDMAM_CH_REGS_BOTH_NAN_MASK_OFFSET    4
#define SDMAM_CH_REGS_DST_NAN_MASK_LEN        1
#define SDMAM_CH_REGS_DST_NAN_MASK_OFFSET     3
#define SDMAM_CH_REGS_SRC_NAN_MASK_LEN        1
#define SDMAM_CH_REGS_SRC_NAN_MASK_OFFSET     2
#define SDMAM_CH_REGS_INPUT_INF_MASK_LEN      1
#define SDMAM_CH_REGS_INPUT_INF_MASK_OFFSET   1
#define SDMAM_CH_REGS_FP_OVERFLOW_MASK_LEN    1
#define SDMAM_CH_REGS_FP_OVERFLOW_MASK_OFFSET 0

#define SDMAM_CH_REGS_DST_RESUME_TIMEOUT_DFX_EN_LEN    1
#define SDMAM_CH_REGS_DST_RESUME_TIMEOUT_DFX_EN_OFFSET 4
#define SDMAM_CH_REGS_SRC_RESUME_TIMEOUT_DFX_EN_LEN    1
#define SDMAM_CH_REGS_SRC_RESUME_TIMEOUT_DFX_EN_OFFSET 3
#define SDMAM_CH_REGS_SQ_LENGTH_DONE_CLR_LEN           1
#define SDMAM_CH_REGS_SQ_LENGTH_DONE_CLR_OFFSET        2
#define SDMAM_CH_REGS_DST_RESUME_TIMEOUT_CLR_LEN       1
#define SDMAM_CH_REGS_DST_RESUME_TIMEOUT_CLR_OFFSET    1
#define SDMAM_CH_REGS_SRC_RESUME_TIMEOUT_CLR_LEN       1
#define SDMAM_CH_REGS_SRC_RESUME_TIMEOUT_CLR_OFFSET    0

#define SDMAM_CH_REGS_DST_FAULT2SLV_DROP_ERR_LEN    1
#define SDMAM_CH_REGS_DST_FAULT2SLV_DROP_ERR_OFFSET 25
#define SDMAM_CH_REGS_SRC_FAULT2SLV_DROP_ERR_LEN    1
#define SDMAM_CH_REGS_SRC_FAULT2SLV_DROP_ERR_OFFSET 24
#define SDMAM_CH_REGS_DFX_CNT_CQ_TLB_B_LEN          4
#define SDMAM_CH_REGS_DFX_CNT_CQ_TLB_B_OFFSET       16
#define SDMAM_CH_REGS_DFX_CNT_CQ_TLB_W_LEN          4
#define SDMAM_CH_REGS_DFX_CNT_CQ_TLB_W_OFFSET       12
#define SDMAM_CH_REGS_DFX_CNT_CQ_TLB_AW_LEN         4
#define SDMAM_CH_REGS_DFX_CNT_CQ_TLB_AW_OFFSET      8
#define SDMAM_CH_REGS_DFX_CNT_SQ_TLB_R_LEN          4
#define SDMAM_CH_REGS_DFX_CNT_SQ_TLB_R_OFFSET       4
#define SDMAM_CH_REGS_DFX_CNT_SQ_TLB_AR_LEN         4
#define SDMAM_CH_REGS_DFX_CNT_SQ_TLB_AR_OFFSET      0

#define SDMAM_CH_REGS_DFX_CNT_ATS_TERMINATE_LEN      4
#define SDMAM_CH_REGS_DFX_CNT_ATS_TERMINATE_OFFSET   28
#define SDMAM_CH_REGS_DFX_CNT_SQTLB_ERR_LEN          4
#define SDMAM_CH_REGS_DFX_CNT_SQTLB_ERR_OFFSET       24
#define SDMAM_CH_REGS_DFX_CNT_DMAA2DMAM_COMP_LEN     4
#define SDMAM_CH_REGS_DFX_CNT_DMAA2DMAM_COMP_OFFSET  20
#define SDMAM_CH_REGS_DFX_CNT_DMAM2DMAA_SQE_LEN      4
#define SDMAM_CH_REGS_DFX_CNT_DMAM2DMAA_SQE_OFFSET   16
#define SDMAM_CH_REGS_DFX_CNT_DMAM2DMAA_REQ_LEN      4
#define SDMAM_CH_REGS_DFX_CNT_DMAM2DMAA_REQ_OFFSET   12
#define SDMAM_CH_REGS_DFX_CNT_SQBUF2TRANS_SET_LEN    4
#define SDMAM_CH_REGS_DFX_CNT_SQBUF2TRANS_SET_OFFSET 8
#define SDMAM_CH_REGS_DFX_CNT_IOE_LEN                4
#define SDMAM_CH_REGS_DFX_CNT_IOE_OFFSET             4
#define SDMAM_CH_REGS_DFX_CNT_IOC_LEN                4
#define SDMAM_CH_REGS_DFX_CNT_IOC_OFFSET             0

#define SDMAM_CH_REGS_DFX_LEN_REMAIN_BIT0_LEN        1
#define SDMAM_CH_REGS_DFX_LEN_REMAIN_BIT0_OFFSET     31
#define SDMAM_CH_REGS_DFX_DST_RESUME_TOUT_LEN        1
#define SDMAM_CH_REGS_DFX_DST_RESUME_TOUT_OFFSET     30
#define SDMAM_CH_REGS_DFX_DST_FAULT_CS_LEN           4
#define SDMAM_CH_REGS_DFX_DST_FAULT_CS_OFFSET        25
#define SDMAM_CH_REGS_DFX_DST_FAULT_TERMINATE_LEN    1
#define SDMAM_CH_REGS_DFX_DST_FAULT_TERMINATE_OFFSET 24
#define SDMAM_CH_REGS_DFX_DST_FAULT_STALL_LEN        1
#define SDMAM_CH_REGS_DFX_DST_FAULT_STALL_OFFSET     23
#define SDMAM_CH_REGS_DFX_DST_FAULT_ABORT_LEN        1
#define SDMAM_CH_REGS_DFX_DST_FAULT_ABORT_OFFSET     22
#define SDMAM_CH_REGS_DFX_SRC_RESUME_TOUT_LEN        1
#define SDMAM_CH_REGS_DFX_SRC_RESUME_TOUT_OFFSET     21
#define SDMAM_CH_REGS_DFX_CQHDB_CFGERR_LEN           1
#define SDMAM_CH_REGS_DFX_CQHDB_CFGERR_OFFSET        20
#define SDMAM_CH_REGS_DFX_SRC_FAULT_CS_LEN           4
#define SDMAM_CH_REGS_DFX_SRC_FAULT_CS_OFFSET        16
#define SDMAM_CH_REGS_DFX_SRC_FAULT_TERMINATE_LEN    1
#define SDMAM_CH_REGS_DFX_SRC_FAULT_TERMINATE_OFFSET 15
#define SDMAM_CH_REGS_DFX_SRC_FAULT_STALL_LEN        1
#define SDMAM_CH_REGS_DFX_SRC_FAULT_STALL_OFFSET     14
#define SDMAM_CH_REGS_DFX_SRC_FAULT_ABORT_LEN        1
#define SDMAM_CH_REGS_DFX_SRC_FAULT_ABORT_OFFSET     13
#define SDMAM_CH_REGS_DFX_TXBUF_SRC_VALID_LEN        1
#define SDMAM_CH_REGS_DFX_TXBUF_SRC_VALID_OFFSET     12
#define SDMAM_CH_REGS_DFX_TXBUF_DST_VALID_LEN        1
#define SDMAM_CH_REGS_DFX_TXBUF_DST_VALID_OFFSET     11
#define SDMAM_CH_REGS_DFX_SPLIT_BUSY_LEN             1
#define SDMAM_CH_REGS_DFX_SPLIT_BUSY_OFFSET          10
#define SDMAM_CH_REGS_DFX_SRC_ATS_REQ_VLD_LEN        1
#define SDMAM_CH_REGS_DFX_SRC_ATS_REQ_VLD_OFFSET     9
#define SDMAM_CH_REGS_DFX_DST_ATS_REQ_VLD_LEN        1
#define SDMAM_CH_REGS_DFX_DST_ATS_REQ_VLD_OFFSET     8
#define SDMAM_CH_REGS_DFX_CQFIFO_FULL_LEN            1
#define SDMAM_CH_REGS_DFX_CQFIFO_FULL_OFFSET         7
#define SDMAM_CH_REGS_DFX_STREAM_BUSY_LEN            1
#define SDMAM_CH_REGS_DFX_STREAM_BUSY_OFFSET         6
#define SDMAM_CH_REGS_DFX_CQFIFO_EMPTY_LEN           1
#define SDMAM_CH_REGS_DFX_CQFIFO_EMPTY_OFFSET        5
#define SDMAM_CH_REGS_DFX_CQTLB_WRING_LEN            1
#define SDMAM_CH_REGS_DFX_CQTLB_WRING_OFFSET         4
#define SDMAM_CH_REGS_DFX_SQTLB_CFGERR_LEN           1
#define SDMAM_CH_REGS_DFX_SQTLB_CFGERR_OFFSET        3
#define SDMAM_CH_REGS_DFX_SQ_QUIESCENT_LEN           1
#define SDMAM_CH_REGS_DFX_SQ_QUIESCENT_OFFSET        2
#define SDMAM_CH_REGS_DFX_IOC_STATUS_LEN             1
#define SDMAM_CH_REGS_DFX_IOC_STATUS_OFFSET          1
#define SDMAM_CH_REGS_DFX_IOE_STATUS_LEN             1
#define SDMAM_CH_REGS_DFX_IOE_STATUS_OFFSET          0

#define SDMAM_CH_REGS_DFX_INF3_LEN    32
#define SDMAM_CH_REGS_DFX_INF3_OFFSET 0

#define SDMAM_CH_REGS_DFX_INF4_LEN    32
#define SDMAM_CH_REGS_DFX_INF4_OFFSET 0

#define SDMAM_CH_REGS_DFX_INF5_LEN           31
#define SDMAM_CH_REGS_DFX_INF5_OFFSET        1
#define SDMAM_CH_REGS_DFX_INF5_QRESET_LEN    1
#define SDMAM_CH_REGS_DFX_INF5_QRESET_OFFSET 0

#define SDMAM_CH_REGS_DFX_INF6_LEN    32
#define SDMAM_CH_REGS_DFX_INF6_OFFSET 0

#define SDMAM_CH_REGS_DFX_INF7_LEN    32
#define SDMAM_CH_REGS_DFX_INF7_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT0_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT0_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT1_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT1_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT2_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT2_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT3_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT3_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT4_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT4_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT5_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT5_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT6_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT6_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT7_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT7_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT8_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT8_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT9_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT9_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT10_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT10_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT11_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT11_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT12_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT12_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT13_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT13_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT14_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT14_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT15_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT15_OFFSET 0

#endif // __SDMAM_CH_REGS_REG_OFFSET_FIELD_H__
